Design and Synthesis of 16-bit ALU using Reversible Logic Gates

The paper describes the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ALU. Using reversible logic gates instead of traditional logic AND/OR gates, a reversible ALU whose function is the same as traditional ALU is constructed. Comparing with the number of input bits and the discarded bits of the traditional ALU, the reversible ALU significantly reduce the use and loss of information bits. The proposed reversible 16-bit ALU reduces the information bits use and loss by reusing the logic information bits logically and realizes the goal of lowering power consumption of logic circuits. Programmable reversible logic gates are realized in Verilog HDL, simulated and synthesized using Cadence NCSIM and RTL complier.